PCI Express Cores

Datasheets :

1. Standard PCIe Core

2. Pro PCIe Core

Touit offers a Standard PCI Express (PCIe) core with low resource utilization and low transmit/receive latencies. The Standard PCIe core handles all of the PCIe layer implementation details with user access to the entire Transaction Layer Packet (TLP). In certain applications, which require optimized to real-time communication, access to the Transaction Layer Packet can be an advantage.

For these more demanding applications, Touit can custom-design the interface to fit your needs, or provide tech/engineer support for those designing their own interfaces.

For general applications, add on Touit's Pro core processing layer with its parallel bus interface to manage TLP details and configure DMA channels.

Using Touit's Pro core interface is similar to using a PCI to local bus bridge chip such as the PLX 905x or AMCC 593x. When migrating an existing design from a PCI bridge chip to PCI Express, often times only a larger FPGA with a SERDES is required.

The FPGA design, interface, and implementation are all simplified with the Touit Pro core. For example: there are no input or output pin timing constraint requirements, no board level routing requirements, no additional power supplies, and one less chip to procure and solder on the board. This can lower the overall board cost and reduce time-to-market.

Our PCI Express cores include device drivers, API, and sample programs. Please contact Touit or refer to the datasheets for more information.

PCIe Core "Pro" Core "Standard" Core
Description
  • Endpoint Controller
  • x1, x4 Lanes
  • No PCI Express knowledge required
  • Quick time-to-market
  • Endpoint Controller
  • x1, x4 Lanes
  • PCI Express knowledge required
  • Access to PCI Express protocols
FPGA Compatability
  • Lattice
  • Xilinx
  • Altera
  • External PHY or internal SERDES
  • Lattice
  • Xilinx
  • Altera
  • External PHY or internal SERDES
Resource Usage Approximately 6500 LUTs and 4500 registers Approximately 4600 LUTs and 3700 registers
Features
  • DMA controller
  • Complete TLP overhead and packet processing
  • Receive and transmit latencies of ~280ns
  • Full duplex communication
  • Up to 8 outstanding requests with timeout control
  • 2kB maximum payload size
  • Receive and transmit latencies of ~200ns
  • Full duplex communication
  • Up to 32 outstanding requests with timeout control
  • 2kB maximum payload size
Advanced PCIe Features
  • End-to-end cyclic redundancy checking (ECRC)
  • Advanced Error Reporting (AER)
  • One Virtual Channel (VC)
  • End-to-end cyclic redundancy checking (ECRC)
  • Advanced Error Reporting (AER)
  • Up to four Virtual Channels (VC)
  • Quality of Service (QOS)
Power Management
  • Legacy PCI power management
  • Active State Power Management (ASPM)
  • Legacy PCI power management
  • Active State Power Management (ASPM)